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infineon technologies 1 4.01 hyb39s512400/800/160at(l) 512mbit synchronous dram 512 mbit synchronous dram preliminary datasheet april ?01 the hyb39s512400/800/160at(l) are four bank synchronous dram?s organized as 4 banks x 32mbit x4, 4 banks x 16mbit x8 and 4 banks x 8mbit x16 respectively. these synchronous devices achieve high speed data transfer rates for cas -latencies by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. the chip is fabricated with infineon?s advanced 0.14 m 512mbit dram process technology. the device is designed to comply with all industry standards set for synchronous dram products, both electrically and mechanically. all of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock. operating the four memory banks in an interleave fashion allows random access operation to occur at higher rate than is possible with standard drams. a sequential and gapless data rate is possible depending on burst length, cas latency and speed grade of the device. auto refresh (cbr) and self refresh operation are supported. these devices operates with a single 3.3v +/- 0.3v power supply. all 512mbit components are housed in tsopii-54 packages. ? high performance: fully synchronous to positive clock edge 0 to 70 c operating temperature four banks controlled by ba0 & ba1 programmable cas latency: 2 & 3 programmable wrap sequence: sequential or interleave programmable burst length: 1, 2, 4, 8 and full page -6 -7 -7.5 -8 units fck 166 143 133 125 mhz tck3 6 7 7.5 8 ns tac3 5 5.4 5.4 6 ns tck2 7.5 7.5 10 10 ns tac2 5.4 5.4 6 6 ns multiple burst read with single write operation automatic and controlled precharge command data mask for read / write control (x4, x8) data mask for byte control (x16) auto refresh (cbr) and self refresh power down and clock suspend mode 8192 refresh cycles / 64 ms (7,8 s) random column address every clk ( 1-n rule) single 3.3v +/- 0.3v power supply lvttl interface versions plastic packages: p-tsopii-54 400mil width (x4, x8, x16) -6 parts for pc166 3-3-3 operation -7 parts for pc133 2-2-2 operation -7.5 parts for pc133 3-3-3 operation -8 parts for pc100 2-2-2 operation
infineon technologies 2 4.01 hyb39s512400/800/160at(l) 512mbit synchronous dram ordering information pin description type speed grade package description hyb 39s512400at-6 pc166-333-520 p-tsop-54-2 (400mil) 166mhz 4b x 32m x 4 sdram hyb 39s512400at-7 pc133-222-520 p-tsop-54-2 (400mil) 143mhz 4b x 32m x 4 sdram hyb 39s512400at-7.5 pc133-333-520 p-tsop-54-2 (400mil) 133mhz 4b x 32m x 4 sdram hyb 39s512400at-8 pc100-222-620 p-tsop-54-2 (400mil) 125mhz 4b x 32m x 4 sdram hyb 39s512800at-6 pc166-333-520 p-tsop-54-2 (400mil) 166mhz 4b x 16m x 8 sdram hyb 39s512800at-7 pc133-222-520 p-tsop-54-2 (400mil) 143mhz 4b x 16m x 8 sdram hyb 39s512800at-7.5 pc133-333-520 p-tsop-54-2 (400mil) 133mhz 4b x 16m x 8 sdram hyb 39s512800at-8 pc100-222-620 p-tsop-54-2 (400mil) 125mhz 4b x 16m x 8 sdram hyb 39s512160at-6 pc166-333-520 p-tsop-54-2 (400mil) 166mhz 4b x 8m x 16 sdram hyb 39s512160at-7 pc133-222-520 p-tsop-54-2 (400mil) 143mhz 4b x 8m x 16 sdram hyb 39s512160at-7.5 pc133-333-520 p-tsop-54-2 (400mil) 133mhz 4b x 8m x 16 sdram hyb 39s512160at-8 pc100-222-620 p-tsop-54-2 (400mil) 125mhz 4b x 8m x 16 sdram hyb39s512xx0atl pc100-xxx-620 p-tsop-54-2 (400mil) low power versions (on request) clk clock input dqx data input /output cke clock enable dqm, ldqm, udqm data mask cs chip select v dd power (+3.3v) ras row address strobe v ss ground cas column address strobe v ddq power for dq ? s (+ 3.3v) we write enable v ssq ground for dq ? s a0-a12 address inputs nc not connected ba0, ba1 bank select
infineon technologies 3 4.01 hyb39s512400/800/160at(l) 512mbit synchronous dram pinouts: pinout for x4, x8 & x16 organised 512m-drams vdd nc vddq nc dq0 vssq nc nc vddq nc dq1 vssq nc vdd nc we cas ras cs ba0 ba1 a10/ap a0 a1 a2 a3 vdd vss nc vssq nc dq3 vddq nc nc vssq nc dq2 vddq nc vss nc dqm clk cke a12 a11 a9 a8 a7 a6 a5 a4 vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 18 19 20 21 22 23 24 25 26 27 vdd dq0 vddq nc dq1 vssq nc dq2 vddq nc dq3 vssq nc vdd nc we cas ras cs ba0 ba1 a10/ap a0 a1 a2 a3 vdd vss dq7 vssq nc dq6 vddq nc dq5 vssq nc dq4 vddq nc vss nc dqm clk cke a12 a11 a9 a8 a7 a6 a5 a4 vss vss dq15 vssq dq14 dq13 vddq dq12 dq11 vssq dq10 dq9 vddq dq8 vss nc udqm clk cke a12 a11 a9 a8 a7 a6 a5 a4 vss vdd dq0 vddq dq1 dq2 vssq dq3 dq4 vddq dq5 dq6 vssq dq7 vdd ldqm we cas ras cs ba0 ba1 a10/ap a0 a1 a2 a3 vdd 128m x 4 64m x 8 32m x 16 tsopii-54 (400 mil x 875 mil, 0.8 mm pitch)
infineon technologies 4 4.01 hyb39s512400/800/160at(l) 512mbit synchronous dram block diagram for 128m x 4 sdram ( 13 / 12 / 2 addressing) memory array bank 1 x4bit memory array bank 2 x4bit memory array bank 3 x4bit column address counter row decoder memory array bank 0 x4bit column decoder sense amplifier &i(o)bus row decoder sense amplifier & i(o) bus row decoder row decoder column decoder sense amplifier & i(o) bus row address buffer column address buffer refresh counter sense amplifier & i(o) bus a0 - a12, ba0, ba1 a0 - a9, ap,a11,a12 , ba0, ba1 column addresses row addresses input buffer output buffer dq0 - dq3 control logic & timing generator clk cke cs ras cas we dqm column decode r colu mn decoder 8192 x 4096 8192 x4096 8192 x 4096 8192 x 4096
infineon technologies 5 4.01 hyb39s512400/800/160at(l) 512mbit synchronous dram block diagram for 64m x 8 sdram ( 13 / 11 / 2 addressing) memory array bank 1 x8bit memory array bank 2 x8bit memory array bank 3 x8bit column address counter row decoder memory array bank 0 x8bit column decoder sense amplifier &i(o)bus row decoder sense amplifier & i(o) bus row decoder row decoder column decoder sense amplifier & i(o) bus row address buffer column address buffer refresh counter sense amplifier & i(o) bus a0 - a12, ba0, ba1 a0 - a9, ap,a11 ba0, ba1 column addresses row addresses input buffer output buffer dq0 - dq7 control logic & timing generator clk cke cs ras cas we dqm column decode r colu mn decoder 8192 x 2048 8192 x2048 8192 x 2048 8192 x 2048
infineon technologies 6 4.01 hyb39s512400/800/160at(l) 512mbit synchronous dram block diagram for 32m x16 sdram ( 13 / 10 / 2 addressing) memory array bank 1 x16bit memory array bank 2 x16bit memory array bank 3 x16bit column address counter row decoder memory array bank 0 x16bit column decoder sense amplifier & i(o) bus row decoder sense amplifier & i(o) bus row decoder row decoder column decoder sense amplifie r&i(o)bus row address buffer column address buffer refresh counter sense amplifier & i(o) bus a0 - a12, ba0, ba1 a0 - a9, ap, ba0, ba1 column addresses row addresses input buffer output buffer dq0 - dq15 control logic & timing generator clk cke cs ras cas we dqmu dqml column decoder column decoder x 1024 x 1024 x 1024 x 1024 8192 8192 8192
infineon technologies 7 4.01 hyb39s512400/800/160at(l) 512mbit synchronous dram signal pin description pin type signal polarity function clk input pulse positive edge the system clock input. all of the sdram inputs are sampled on the rising edge of the clock. cke input level active high activates the clk signal when high and deactivates the clk signal when low, thereby initiates either the power down mode, suspend mode, or the self refresh mode. cs input pulse active low cs enables the command decoder when low and disables the command decoder when high. when the command decoder is disabled, new commands are ignored but previous operations continue. ras cas we input pulse active low when sampled at the positive rising edge of the clock, cas , ras , and we define the command to be executed by the sdram. a0 - a12 input level ? during a bank activate command cycle, a0-a12 define the row address (ra0-ra12) when sampled at the rising clock edge. during a read or write command cycle, a0-an define the column address (ca0-can) when sampled at the rising clock edge.can depends from the sdram organization: 128m x4 sdram can = ca9, ca11;ca12 (page length = 4096 bits) 64m x8 sdram can = ca9, ca11 (page length = 2048 bits) 32m x16 sdram can = ca9 (page length = 1024 bits) in addition to the column address, a10(= ap) is used to invoke autoprecharge operation at the end of the burst read or write cycle. if a10 is high, autoprecharge is selected and ba0, ba1 defines the bank to be precharged. if a10 is low, autoprecharge is disabled. during a precharge command cycle, a10 (= ap) is used in conjunction with ba0 and ba1 to control which bank(s) to precharge. if a10 is high, all four banks will be precharged regardless of the state of ba0 and ba1. if a10 is low, then ba0 and ba1 are used to define which bank to precharge. ba0, ba1 input level ? bank select inputs. bank address inputs selects which of the four banks a command applies to. dqx input output level ? data input/output pins operate in the same manner as on conventional drams.
infineon technologies 8 4.01 hyb39s512400/800/160at(l) 512mbit synchronous dram dqm ldqm udqm input pulse active high the data input/output mask places the dq buffers in a high impedance state when sampled high. in read mode, dqm has a latency of two clock cycles and controls the output buffers like an output enable. in write mode, dqm has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the write operation if dqm is high. one dqm input it present in x4 and x8 sdrams, ldqm and udqm controls the lower and upper bytes in x16 sdrams. v dd v ss supply ?? power and ground for the input buffers and the core logic. v ddq v ssq supply ?? isolated power supply and ground for the output buffers to provide improved noise immunity. pin type signal polarity function
infineon technologies 9 4.01 hyb39s512400/800/160at(l) 512mbit synchronous dram operation definition all of sdram operations are defined by states of control signals cs , ras , cas , we , and dqm at the positive edge of the clock. the following list shows the truth table for the operation commands. operation device state cke n-1 cke n dqm ba0 ba1 ap= a10 addr . cs ras cas we bank active idle 3 hxxvvvllhh bank precharge any h x x v l x l l h l precharge all any h x x x h x l l h l write active 3 hxxvlvlhll write with autoprecharge active 3 hxxvhvlhll read active 3 hxxvlvlhlh read with autoprecharge active 3 hxxvhvlhlh mode register set idle h x x v v v l l l l no operation any h x x x x x l h h h burst stop active h x x x x x l h h l device deselect any hxxxxxhxxx auto refresh idle h h x x x x l l l h self refresh entry idle h l x x x x l l l h self refresh exit idle (self refr.) lhxxxx hxxx lhhx clock suspend entry active h l x x x x x x x x power down entry (precharge or active standby) idle hlxxxx hxxx active 4 lhhh clock suspend exit active l h x x x x x x x x power down exit any (power down) lhxxxx hxxx lhhl data write/output enable active h x l x x x x x x x data write/output disable active h x h x x x x x x x notes 1. v = valid, x = don ? t care, l = low level, h = high level 2. cken signal is input level when commands are provided, cken-1 signal is input level one clock before the commands are provided. 3. this is the state of the banks designated by ba0, ba1 signals. 4. power down mode can not be entered in a burst cycle. when this command asserted in the burst mode cycle device is in clock suspend mode.
infineon technologies 10 4.01 hyb39s512400/800/160at(l) 512mbit synchronous dram mode registere set table a11 a3 a4 a2 a1 a0 a10 a9 a8 a7 a6 a5 address bus (ax) bt burst length cas latency mode register (mx) cas latency m6 m5 m4 latency 000reserved 001reserved 010 2 011 3 100 reserved 101 110 111 burst length m2 m1 m0 length sequential interleave 000 1 1 001 2 2 010 4 4 011 8 8 100 reserved reserved 101 110 111full page burst type m3 type 0 sequential 1 interleave operation mode m9 mode 0 burst read / burst write 1 burst read / single write operation mode ba0 ba1 a12
infineon technologies 11 4.01 hyb39s512400/800/160at(l) 512mbit synchronous dram power on and initialization the default power on state of the mode register is supplier specific and may be undefined. the following power on and initialization sequence guarantees the device is preconditioned to each users specific needs. like a conventional dram, the synchronous dram must be powered up and initialized in a predefined manner.during power on, all vdd and vddq pins must be built up simultaneously to the specified voltage when the input signals are held in the ? nop ? state. the power on voltage must not exceed vdd+0.3v on any of the input pins or vdd supplies. the clk signal must be started at the same time. after power on, an initial pause of 200 s is required followed by a precharge of all banks using the precharge command. to prevent data contention on the dq bus during power on, it is required that the dqm and cke pins be held high during the initial pause period. once all banks have been precharged, the mode register set command must be issued to initialize the mode register. a minimum of eight auto refresh cycles (cbr) are also required.these may be done before or after programming the mode register. failure to follow these steps may lead to unpredictable start-up modes. programming the mode register the mode register designates the operation mode at the read or write cycle. this register is divided into 4 fields. a burst length field to set the length of the burst, an addressing selection bit to program the column access sequence in a burst cycle (interleaved or sequential), a cas latency field to set the access time at clock cycle and a operation mode field to differentiate between normal operation (burst read and burst write) and a special burst read and single write mode. the mode set operation must be done before any activate command after the initial power up. any content of the mode register can be altered by re-executing the mode set command. all banks must be in precharged state and cke must be high at least one clock before the mode set operation. after the mode register is set, a standby or nop command is required. low signals of ras , cas , and we at the positive edge of the clock activate the mode set operation. address input data at this timing defines parameters to be set as shown in the previous table. read and write operation when ras is low and both cas and we are high at the positive edge of the clock, a ras cycle starts. according to address data, a word line of the selected bank is activated and all of sense amplifiers associated to the wordline are set. a cas cycle is triggered by setting ras high and cas low at a clock timing after a necessary delay, t rcd , from the ras timing. we is used to define either a read (we = h) or a write (we = l) at this stage. sdram provides a wide variety of fast access modes. in a single cas cycle, serial data read or write operations are allowed at up to a 166 mhz data rate. the numbers of serial data bits are the burst length programmed at the mode set operation, i.e., one of 1, 2, 4 and 8 and full page. column addresses are segmented by the burst length and serial data accesses are done within this boundary. the first column address to be accessed is supplied at the cas timing and the subsequent addresses are generated automatically by the programmed burst length and its sequence. for example, in a burst length of 8 with interleave sequence, if the first address is ? 2 ? , then the rest of the burst sequence is 3, 0, 1, 6, 7, 4, and 5. full page burst operation is only possible using the sequential burst type and page length is a function of the i/o organisation and column addressing. full page burst operation does not self terminate once the burst length has been reached. in other words, unlike burst length of 2, 4 and 8, full page burst continues until it is terminated using another command.
infineon technologies 12 4.01 hyb39s512400/800/160at(l) 512mbit synchronous dram similar to the page mode of conventional dram ? s, burst read or write accesses on any column address are possible once the ras cycle latches the sense amplifiers. the maximum t ras or the refresh interval time limits the number of random column accesses. a new burst access can be done even before the previous burst ends. the interrupt operation at every clock cycle is supported. when the previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst length. an interrupt which accompanies an operation change from a read to a write is possible by exploiting dqm to avoid bus contention. when two or more banks are activated sequentially, interleaved bank read or write operations are possible. with the programmed burst length, alternate access and precharge operations on two or more banks can realize fast serial data access modes among many different pages. once two or more banks are activated, column to column interleave operation can be performed between different pages. burst length and sequence: refresh mode sdram has two refresh modes, auto refresh and self refresh. auto refresh is similar to the cas -before-ras refresh of conventional drams. all of banks must be precharged before applying any refresh mode. an on-chip address counter increments the word and the bank addresses and no bank information is required for both refresh modes. the chip enters the auto refresh mode, when ras and cas are held low and cke and we are held high at a clock timing. the mode restores word line after the refresh and no external precharge command is necessary. a minimum trc time is required between two automatic refreshes in a burst refresh mode. the same rule applies to any access command after the automatic refresh operation. burst length starting address (a2 a1 a0) sequential burst addressing (decimal) interleave burst addressing (decimal) 2 xx0 xx1 0, 1 1, 0 0, 1 1, 0 4x00 x01 x10 x11 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0 8 000 001 010 011 100 101 110 111 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 2 3 4 5 6 7 0 1 3 4 5 6 7 0 1 2 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 1 0 3 2 5 4 7 6 2 3 0 1 6 7 4 5 3 2 1 0 7 6 5 4 4 5 6 7 0 1 2 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0 full page nnn cn, cn+1, cn+2....... not supported
infineon technologies 13 4.01 hyb39s512400/800/160at(l) 512mbit synchronous dram the chip has an on-chip timer and the self refresh mode is available. the mode restores the word lines after ras , cas , and cke are low and we is high at a clock timing. all of external control signals including the clock are disabled. returning cke to high enables the clock and initiates the refresh exit operation. after the exit command, at least one trc delay is required prior to any access command. dqm function dqm has two functions for data i/o read and write operations. during reads, when it turns to ? high ? at a clock timing, data outputs are disabled and become high impedance after two clock delay (dqm data disable latency t dqz ). it also provides a data mask function for writes. when dqm is activated, the write operation at the next clock is prohibited (dqm write mask latency t dqw = zero clocks). suspend mode during normal access mode, cke is held high enabling the clock. when cke is low, it freezes the internal clock and extends data read and write operations. one clock delay is required for mode entry and exit (clock suspend latency t csl ). power down in order to reduce standby power consumption, a power down mode is available. all banks must be precharged and the necessary precharge delay (trp) must occur before the sdram can enter the power down mode. once the power down mode is initiated by holding cke low, all of the receiver circuits except clk and cke are gated off. the power down mode does not perform any refresh operations, therefore the device can ? t remain in power down mode longer than the refresh period (tref) of the device. exit from this mode is performed by taking cke ? high ? . one clock delay is required for power down mode entry and exit. auto precharge two methods are available to precharge sdrams. in an automatic precharge mode, the cas timing accepts one extra address, ca10, to determine whether the chip restores or not after the operation. if ca10 is high when a read command is issued, the read with auto-precharge function is initiated. if ca10 is high when a write command is issued, the write with auto- precharge function is initiated. the sdram automatically enters the precharge operation a time delay equal to t wr ( ? write recovery time ? ) after the last data in. precharge command there is also a separate precharge command available. when ras and we are low and cas is high at a clock timing, it triggers the precharge operation. three address bits, ba0, ba1 and a10 are used to define banks as shown in the following list. the precharge command can be imposed one clock before the last data out for cas latency = 2 and two clocks before the last data out for cas latency = 3. writes require a time delay twr ( ? write recovery time ? ) of 2 clocks minimum from the last data out to apply the precharge command.
infineon technologies 14 4.01 hyb39s512400/800/160at(l) 512mbit synchronous dram bank selection by address bits burst termination once a burst read or write operation has been initiated, there are several methods in which to terminate the burst operation prematurely. these methods include using another read or write command to interrupt an existing burst operation, use a precharge command to interrupt a burst cycle and close the active bank, or using the burst stop command to terminate the existing burst operation but leave the bank open for future read or write commands to the same page of the active bank. when interrupting a burst with another read or write command care must be taken to avoid dq contention. the burst stop command, however, has the fewest restrictions making it the easiest method to use when terminating a burst operation before it has been completed. if a burst stop command is issued during a burst write operation, then any residual data from the burst write cycle will be ignored. data that is presented on the dq pins before the burst stop command is registered will be written to the memory. capacitance t a = 0 to 70 c; v dd = 3.3 v 0.3 v, f = 1 mhz a10 ba0 ba1 0 0 0 bank 0 0 0 1 bank 1 0 1 0 bank 2 0 1 1 bank 3 1xx all banks parameter symbol values unit min. max. input capacitance (clk) c i 1 2.5 3.5 pf input capacitance (a0-a12, ba0,ba1,ras , cas , we , cs , cke, dqm) c i 2 2.5 3.8 pf input / output capacitance (dq) c i o 4.0 6.0 pf
infineon technologies 15 4.01 hyb39s512400/800/160at(l) 512mbit synchronous dram absolute maximum ratings recommended operation conditions and dc eletrical characteristics t a = 0 to 70 o c; parameter symbol limit values unit min. max. input / output voltage relative to v ss v in, v out ? 1.0 4.6 v power supply voltage v dd, v ddq ? 1.0 4.6 v operating temperature t a 0+70 o c storage temperature range t stg -55 +150 o c power dissipation per sdram component p d ? 1w data out current (short circuit) i os ? 50 ma permanent device damage may occur if ? absolute maximum ratings ? are exceeded. functional operation should be restricted to recommended operation conditions. exposure to higher than recommended voltage for extended periods of time affect device reliability parameter symbol limit values unit notes min. typ. max. supply voltage v dd, v ddq 3.0 3.3 3.6 v 1 input high voltage v ih 2.0 3.0 v ddq +0.3 v 1, 2 input low voltage v il ? 0.3 0 0.8 v 1, 2 output high voltage ( i out = ? 4.0 ma) v oh 2.4 ?? v1 output low voltage ( i out = 4.0 ma) v ol ?? 0.4 v 1 input leakage current, any input (0 v < v in < v dd , all other inputs = 0 v) i il ? 5 ? 5ma output leakage current (dqs are disabled, 0 v < v out < v ddq ) i ol ? 5 ? 5ma notes: 1. all voltages are referenced to v ss . 2. vih may overshoot to v ddq + 2.0 v for pulse width of < 4ns with 3.3v. vil may undershoot to -2.0 v for pulse width < 4.0 ns with 3.3v. pulse width measured at 50% points with amplitude measured peak to dc reference.
infineon technologies 16 4.01 hyb39s512400/800/160at(l) 512mbit synchronous dram operating currents (t a = 0 to 70 o c, vdd = 3.3v 0.3v) (recommended operating conditions unless otherwise noted) parameter & test condition symb. -6 -7/-7.5 -8 note max. operating current all banks operated in random access, all banks operated in ping-pong manner icc1 315 270 225 ma 3 precharge standby current in power down mode cs =vih (min.), cke<=vil(max) icc2p 444ma3 precharge standby current in non-power down mode cs = vih (min.), cke>=vih(min) icc2n 42 36 30 ma 3 no operating current cs = vih(min), active state ( max. 4 banks) cke >=vih(min.) icc3n 40 35 30 ma 3 cke <=vil(max.) icc3p 11 11 11 ma 3 burst operating current read command cycling icc4 285 255 150 ma 3,4 auto refresh current trc=trcmin., auto refresh command cycling icc5 480 440 360 ma 3 self refresh current self refresh mode, cke=0.2v standard version icc6 444ma3 l-version tbd tbd tmb m a notes: 3. these parameters depend on the cycle rate. all values are measured at 166 mhz for ? -6 ? , at 133 mhz for ? -7 ? and ? -7.5 ? and at 100 mhz for ? -8 ? component with the outputs open. input signals are changed once during tck. 4. these parameters are measured with continuous data stream during read access and all dq toggling. cl=3 and bl=4 is assumed and the vddq current is excluded.
infineon technologies 17 4.01 hyb39s512400/800/160at(l) 512mbit synchronous dram ac characteristics 1)2) t a = 0 to 70 o c; v ss = 0 v; v dd, v ddq = 3.3 v 0.3 v, t t = 1 ns parameter symbol limit values unit -6 pc166- 333 -7 pc133- 222 -7.5 pc133- 333 -8 pc100- 222 min. max. min. max. min. max. min. max. clock and clock enable clock cycle time cas latency = 3 cas latency = 2 t ck 6 7.5 ? ? 7 7.5 ? ? 7.5 10 ? ? 8 10 ? ? ns ns clock frequency cas latency = 3 cas latency = 2 t ck ? ? 166 133 ? ? 143 133 ? ? 133 100 ? ? 125 100 mhz mhz access time from clock cas latency = 3 cas latency = 2 t ac ? ? 5 5.4 ? ? 5.4 5.4 ? ? 5.4 6 ? ? 6 6 ns ns 2, 3, 6 clock high pulse width t ch 2 ? 2.5 ? 2.5 ? 3 ? ns clock low pulse width t cl 2 ? 2.5 ? 2.5 ? 3 ? ns transition time t t 0.3 1.2 0.3 1.2 0.3 1.2 0.5 10 ns setup and hold times input setup time t is 1.4 ? 1.5 ? 1.5 ? 2 ? ns 4 input hold time t ih 0.7 ? 0.8 ? 0.8 ? 1 ? ns 4 cke setup time t cks 1.4 ? 1.5 ? 1.5 ? 2 ? ns 4 cke hold time t ckh 0.7 ? 0.8 ? 0.8 ? 1 ? ns 4 mode register set-up time t rsc 2 ? 2 ? 2 ? 2 ? clk power down mode entry time t sb 060707.508ns common parameters row to column delay time t rcd 15 ? 15 ? 20 ? 20 ? ns 5 row precharge time t rp 15 ? 15 ? 20 ? 20 ? ns 5 row active time t ras 36 100k 37 100k 45 100k 48 100k ns 5 row cycle time t rc 60 ? 60 ? 67 ? 70 ? ns 5 row cycle time during auto refresh t rcf 60 63 67 70 ns
infineon technologies 18 4.01 hyb39s512400/800/160at(l) 512mbit synchronous dram activate(a) to activate(b) command period t rrd 12 ? 14 ? 15 ? 16 ? ns 5 cas (a) to cas (b) command period t ccd 1 ? 1 ? 1 ? 1 ? clk refresh cycle refresh period (8192 cycles) t ref ? 64 ? 64 ? 64 ? 64 ms self refresh exit time t srex 1 ? 1 ? 1 ? 1clk read cycle data out hold time t oh 2.5 ? 3 ? 3 ? 3 ? ns 2, 6 data out to low impedance time t lz 1 ? 1 ? 1 ? 0 ? ns data out to high impedance time t hz 36373738ns dqm data out disable latency t dqz ? 2 ? 2 ? 2 ? 2clk write cycle last data input to precharge (write without autoprecharge) t wr 12 ? 12 ? 12 ? 12 ? ns 7 last data input to activate (write with autoprecharge) t dal,min (twr/tck) + (trp/tck) ns 8 dqm write mask latency t dqw 0 ? 0 ? 0 ? 0 ? clk parameter symbol limit values unit -6 pc166- 333 -7 pc133- 222 -7.5 pc133- 333 -8 pc100- 222 min. max. min. max. min. max. min. max.
infineon technologies 19 4.01 hyb39s512400/800/160at(l) 512mbit synchronous dram notes 1. for proper power-up see the operation section of this data sheet. 2. ac timing tests for lv-ttl versions have v il = 0.4 v and v ih = 2.4 v with the timing referenced to the 1.4 v crossover point. the transition time is measured between v ih and v il . all ac measurements assume t t = 1 ns with the ac output load circuit shown in figure below. specified t ac and t oh parameters are measured with a 50 pf only, without any resistive termination and with a input signal of 1v / ns edge rate between 0.8 v and 2.0 v. 3. if clock rising time is longer than 1 ns, a time ( t t /2 ? 0.5) ns has to be added to this parameter. 4. if t t is longer than 1 ns, a time ( t t ? 1) ns has to be added to this parameter. 5. these parameter account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the number of clock cycle = specified value of timing period (counted in fractions as a whole number) 6. access time from clock t ac is 4.6 ns for pc133 components with no termination and 0 pf load, data out hold time t oh is 1.8 ns for pc133 components with no termination and 0 pf load. 7. the write recovery time twr = 12 ns cycles allows to use one clock cycle between the last data- in and the precharge command for frequencies equal or lower than 83 mhz. for operation frequencies higher than 83 mhz two clocks are neccessary between the last data-in and the precharge command.i nfineon recommends to use two clocks for twr for all operation frequencies. 8. when a write command with autoprecharge has been issued a time of tdal(min) has be fullfilled before the next activate command can be applied. for each of the terms, if not allready an integer, round up to the next highest integer. tck is equal to the actual system clock time 50 pf i/o measurement conditions for t ac and t oh clock 2.4 v 0.4 v input is t t t output 1.4 v t lz ac t t ac oh t hz t 1.4 v cl t ch t ih t 1.4 v io.vsd
infineon technologies 20 4.01 hyb39s512400/800/160at(l) 512mbit synchronous dram package outlines gpx09039 22.22 ?.13 1) 127 54 28 0.35 +0.1 -0.05 0.1 1 0.1 10.16 ?.13 ?.2 11.76 ?.1 0.5 does not include plastic or metal protrusion of 0.15 max per side 1) 54x ?.05 ?.05 0.15 -0.03 +0.06 15? ?? 15? ?? 6 max 2.5 max 2) 3) does not include plastic protrusion of 0.25 max per side 2) does not include dambar protrusion of 0.13 max per side 3) index marking 0.8 20.8 26x 0.8 = 0.2 m 54x plastic package p-tsopii-54 (400 mil, 0.8 mm lead pitch) thin small outline package, smd
hyb39s512400/800/16at(l) 512-mbit synchronous dram infineon technologies 21 timing diagrams 1. bank activate command cycle 2. burst read operation 3. read interrupted by a read 4. read to write interval 4.1 read to write interval 4.2 minimum read to write interval 4.3 non-minimum read to write interval 5. burst write operation 6. write and read interrupt 6.1 write interrupted by a write 6.2 write interrupted by read 7. burst write & read with auto-precharge 7.1 burst write with auto-precharge 7.2 burst read with auto-precharge 8. ac- parameters 8.1 ac parameters for a write timing 8.2 ac parameters for a read timing 9. mode register set 10. power on sequence and auto refresh (cbr) 11. clock suspension (using cke) 11. 1 clock suspension during burst read cas latency = 2 11. 2 clock suspension during burst read cas latency = 3 11. 3 clock suspension during burst write cas latency = 2 11. 4 clock suspension during burst write cas latency = 3 12. power down mode and clock suspend 13. self refresh ( entry and exit ) 14. auto refresh ( cbr ) 15. random column read ( page within same bank) 15.1 cas latency = 2 15.2 cas latency = 3 16. random column write ( page within same bank) 16.1 cas latency = 2 16.2 cas latency = 3 17. random row read ( interleaving banks) with precharge 17.1 cas latency = 2 17.2 cas latency = 3 18. random row write ( interleaving banks) with precharge 18.1 cas latency = 2 18.2 cas latency = 3 19. precharge termination of a burst 20. full page burst operation 20.1 full page burst read, cas latency = 2 18.2 full page burst write, cas latency = 3
hyb39s512400/800/16at(l) 512-mbit synchronous dram infineon technologies 22 1. bank activate command cycle 2. burst read operation rc "h" or "l" t t0 (cas latency = 3) bank b row addr. activate bank b address command clk t nop nop rcd t t1 col. addr. bank b with auto precharge write b t spt03784 bank b row addr. activate bank b row addr. bank a activate bank a t nop rrd t tt spt03712 clk read a nop t0 t1 t2 t3 t4 t5 t6 t7 t8 command nop nop nop nop nop nop nop dout a3 ck2 latency = 2 t , dq?s dout a1 dout a0 dout a2 dout a2 ck3 latency = 3 t , dq?s dout a0 dout a1 dout a3 (burst length = 4, cas latency = 2, 3) cas cas
hyb39s512400/800/16at(l) 512-mbit synchronous dram infineon technologies 23 3. read interrupted by a read 4. read to write interval 4.1 read to write interval spt03713 clk read a t0 t1 t2 t3 t4 t5 t6 t7 t8 command dout a0 dout b0 dout b1 dout b2 nop nop nop nop nop nop nop latency = 2 , dq?s ck2 t ck3 latency = 3 t , dq?s (burst length = 4, cas latency = 2, 3) cas cas read b dout b3 dout b1 dout a0 dout b0 dout b3 dout b2 commands = 4 + 1 = 5 cycles minimum delay between the read and write dout a0 dq?s (burst length = 4, cas latency = 3) dqmx command clk nop read a t0 t1 nop nop t2 t3 the write command must be hi-z before din b0 din b1 spt03787 din b2 dqw nop dqz t nop t t4 t5 write b nop t6 t7 nop t8 "h" or "l" write latency of dqmx
hyb39s512400/800/16at(l) 512-mbit synchronous dram infineon technologies 24 4 2. minimum read to write interval 4. 3. non-minimum read to write interval the write command must be hi-z before activate cas ck2 latency = 2 t , dq?s (burst length = 4, cas latency = 2) clk dqm command nop t0 t1 bank a nop dqz t t2 t3 din a0 din a1 din a2 spt03939 din a3 1 clk interval read a write a t4 t5 nop nop t6 t7 nop t8 "h" or "l" t dqw nop cas latency = 3 ck3 cas ck2 latency = 2 t t , dq?s , dq?s dout a0 (burst length = 4, cas latency = 2, 3) clk dqm command nop read a t0 t1 nop nop t2 t3 the write command must be hi-z before dout a0 dout a1 din b0 din b0 din b1 din b1 spt03940 din b2 din b2 read a dqz t nop t4 t5 write b nop t6 t7 nop t8 "h" or "l" t dqw
hyb39s512400/800/16at(l) 512-mbit synchronous dram infineon technologies 25 5. burst write operation extra data is ignored after termination of a burst. din a3 t4 are registered on the same clock edge. the first data element and the write nop (burst length = 4, cas latency = 2, 3) t0 command dq?s clk din a1 t2 nop din a0 write a t1 din a2 nop t3 spt03790 t6 nop nop t5 nop nop t7 nop t8 don?t care
hyb39s512400/800/16at(l) 512-mbit synchronous dram infineon technologies 26 6. write and read interrupt 6.1 write interrupted by a write 6.2 write interrupted by a read 1 clk interval spt03791 clk t0 t1 t2 t3 t4 t5 t6 t7 t8 command nop nop nop nop nop nop dq?s (burst length = 4, cas latency = 2, 3) nop write a din a0 din b0 din b1 din b2 din b3 write b 1 clk interval t5 nop dout b1 dout b0 input data for the write is ignored. , dq?s latency = 3 ck3 cas t don?t care din a0 don?t care (burst length = 4, cas latency = 2, 3) clk , dq?s command latency = 2 ck2 cas t nop t0 din a0 write a don?t care read b t1 t2 dout b0 nop nop t4 t3 spt03719 appears on the outputs to avoid data contention. dout b2 input data must be removed from the dq?s at least one clock cycle before the read data dout b1 dout b3 nop dout b3 nop dout b2 t6 t7 nop t8
hyb39s512400/800/16at(l) 512-mbit synchronous dram infineon technologies 27 7. burst write and read with auto precharge 7.1 burst write with auto-precharge 7.2 burst read with auto-precharge spt03909 2 clk active nop t0 t1 t2 t3 t4 t5 t6 t7 t8 command nop nop nop nop dq?s bank a begin auto precharge bank can be reactivated after trp write a auto precharge din a1 din a0 din a1 din a0 cas latency = 2: dq?s cas latency = 3: wr t wr t rp t rp t * * * active nop command nop nop nop nop nop nop bank a write a au to prech arge nop activate (burst length = 2, cas latency = 2, 3 ) activate spt03721_2 clk with ap nop t0 t1 t2 t3 t4 t5 t6 t7 t8 command dout a0 dout a1 dout a2 dout a3 nop nop nop nop nop nop nop latency = 2 dq?s dout a3 latency = 3 dout a1 dout a0 dout a2 (burst length = 4, cas latency = 2, 3) cas cas read a bank can be reactivated after trp begin auto precharge dq?s rp t * * * t rp
hyb39s512400/800/16at(l) 512-mbit synchronous dram infineon technologies 28 8. ac parameters 8.1 ac parameters for a write timing auto precharge bank b command write with activate write with activate bank a command auto precharge bank a command command bank b addr. ap dqm dq bs hi-z rcd t ax2 ax1 ax0 ax3 rc t rax t as t ah rbx cax command spt03910_2 bx1 bx0 cbx t8 precharge begin auto bank a clk we cas ras cs cke ck2 t cs t ch cks t ch t t cl t t3 t0 t2 t1 t4 t5 t7 t6 t18 burst length = 4, cas latency = 2 t13 t9 t10 t12 t11 t14 t15 t17 t16 t19 t20 t22 t21 rbx rax activate write command bank a bank a ds t t dh ray bank b precharge begin auto rby activate precharge command bank a bank a command activate bank b command t wr t ckh raz raz rby ray ray bx2 bx3 t wr rp t ay2 ay1 ay0 ay3 rp t rrd t
hyb39s512400/800/16at(l) 512-mbit synchronous dram infineon technologies 29 8.2 ac parameters for a read timing ac2 hi-z dq activate command bank a read bank a command dqm addr. ap t rcd t lz t t as rax rax t ah cax rrd t command bank b read with auto precharge activate bank b command ax1 ax0 bx0 activate spt03911_2 command bank a bx1 t ac2 oh t hz t t ras rc t rbx rbx rbx hz t ray ray t5 t t bs we cas ras t cs cke cks t ch t t cs ch cl ck2 clk t0 t1 t2 t3 t4 precharge bank b begin auto t ckh burst length = 2, cas latency = 2 t6 t7 t8 t10 t9 t11 t13 t12 rp t precharge bank a command
hyb39s512400/800/16at(l) 512-mbit synchronous dram infineon technologies 30 9. mode register set set command mode register all banks precharge command any command address key t0 t1 t2 t8 rsc t t4 t3 t5 t6 t7 t11 t9 t10 t12 t13 spt03912_2 t19 t16 t15 t14 t17 t18 cas latency = 2 t20 t21 t22 bs addr. ap cs we cas ras cke clk
hyb39s512400/800/16at(l) 512-mbit synchronous dram infineon technologies 31 10. power on sequence and auto refresh (cbr) inputs must be 200 stable for s dqm ap dq addr. bs rp command all banks precharge hi-z ~ ~ t 1st auto refresh command ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ spt03913 mode register set command address key 8th auto refresh command ~ ~ t rc ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ command any minimum of 8 refresh cycles are required t8 we cas ras cs cke clk required ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ t3 is ~ ~ ~ ~ level high t0 t2 t1 t5 t4 t7 t6 t18 2 clock min. ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ t13 ~ ~ ~ ~ t10 t9 t12 t11 t14 t15 t17 t16 t20 t19 t22 t21
hyb39s512400/800/16at(l) 512-mbit synchronous dram infineon technologies 32 11. clock suspension ( using cke) 11.1 clock suspension during burst read cas latency = 2 command bank a dqm addr. dq ap bs read command bank a activate hi-z suspend 1 cycle clock ax0 csl t ax1 cax rax rax spt03914 t suspend 3 cycles suspend 2 cycles clock ax2 csl t clock ax3 hz t7 we cas ras cs cke clk ck2 t t0 t1 t2 t3 t4 t6 t5 t16 t8 t9 t10 t11 t14 t12 t13 t15 burst length = 4, cas latency = 2 t18 t17 t19 t20 t21 t22 csl t
hyb39s512400/800/16at(l) 512-mbit synchronous dram infineon technologies 33 11.2 clock suspension during burst read cas latency = 3 csl dqm addr. dq ap bs bank a activate command hi-z command bank a read ax0 t rax rax cax hz t t suspend 1 cycle clock suspend 2 cycles clock csl ax1 ax2 clock suspend 3 cycles t csl ax3 spt03915 t7 we cas ras cs cke clk ck3 t t0 t1 t2 t3 t4 t6 t5 t16 t8 t9 t10 t11 t14 t12 t13 t15 burst length = 4, cas latency = 3 t18 t17 t19 t20 t21 t22
hyb39s512400/800/16at(l) 512-mbit synchronous dram infineon technologies 34 11.3 clock suspension during burst write cas latency = 2 bank a dqm addr. dq ap bs dax0 command write activate command bank a hi-z clock clock 1 cycle suspend suspend 2 cycles dax1 cax rax rax dax3 clock suspend 3 cycles dax2 spt03916 t7 we cas ras cs cke clk ck2 t t0 t1 t2 t3 t4 t6 t5 t16 t8 t9 t10 t11 t14 t12 t13 t15 burst length = 4, cas latency = 2 t18 t17 t19 t20 t21 t22
hyb39s512400/800/16at(l) 512-mbit synchronous dram infineon technologies 35 11.4 clock suspension during burst write cas latency = 3 clock suspend 2 cycles bank a dqmx addr. dq a8/ap ba activate command bank a hi-z clock 1 cycle suspend command write dax0 dax1 rax rax cax clock suspend 3 cycles dax2 dax3 spt03917 t7 we cas ras cs cke clk ck3 t t0 t1 t2 t3 t4 t6 t5 t16 t8 t9 t10 t11 t14 t12 t13 t15 burst length = 4, cas latency = 3 t18 t17 t19 t20 t21 t22
hyb39s512400/800/16at(l) 512-mbit synchronous dram infineon technologies 36 12. power down mode and clock suspend bs clock suspend clock suspend mode entry mode exit addr. dqm dq ap standby active activate bank a command hi-z read command bank a rax rax cax power down power down mode exit mode entry spt03918 end clock mask clock mask start ax0 ax1 ax2 precharge command bank a ax3 t hz precharge standby any command t7 cas we ras cs cke clk ck2 t t0 t1 t2 cks t t3 t4 t6 t5 t16 t8 t9 t10 t11 t14 t12 t13 t15 burst length = 4, cas latency = 2 cks t t18 t17 t19 t20 t21 t22
hyb39s512400/800/16at(l) 512-mbit synchronous dram infineon technologies 37 13. self refresh (entry and exit) bs t self refresh exit command issued addr. dqm dq ap entry self refresh must be idle all banks hi-z spt03919-2 exit command begin self refresh srex t rc self refresh command exit any t7 cs cas we ras cke clk t cks t0 t1 t2 t3 t4 t6 t5 t16 cks t t8 t9 t10 t11 t14 t12 t13 t15 t18 t17 t19 t20 t21 t22 *) *) minimum ras cycle time depends on cas latency and trc ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
hyb39s512400/800/16at(l) 512-mbit synchronous dram infineon technologies 38 14. auto refresh (cbr) (minimum interval) addr. dqm dq ap bs auto refresh command all banks precharge command hi-z t rp t rc spt03920_2 rc t rax rax cax t7 we cas ras cs cke clk ck2 t t0 t1 t2 t3 t4 t6 t5 t16 t8 t9 t10 t11 t14 t12 t13 t15 burst length = 4, cas latency = 2 t18 t17 t19 t20 t21 t22 command auto refresh command command bank a activate bank a read ax2 ax0 ax1 ax3
hyb39s512400/800/16at(l) 512-mbit synchronous dram infineon technologies 39 15. random column read (page within same bank) 15.1 cas latency = 2 ay1 addr. bs dq dqm ap activate command z hi bank a raw raw command read command bank a read bank a aw0 aw1 caw cax read bank a command aw3 aw2 ax0 ax1 ay0 cay cs we cas ras cke clk t0 ck2 t t1 t2 t8 t4 t3 t5 t6 t7 t11 t9 t10 t12 t13 precharge command bank a ay2 ay3 activate command bank a raz raz spt03921 read bank a command caz burst length = 4, cas latency = 2 t19 t16 t15 t14 t17 t18 t20 t21 t22 az3 az0 az1 az2
hyb39s512400/800/16at(l) 512-mbit synchronous dram infineon technologies 40 15.2 cas latency = 3 ay3 caw addr. bs dq dqm ap z hi bank a activate command read command bank a raw raw bank a command aw1 aw0 read bank a command aw2 aw3 cax read ax1 ax0 ay0 precharge command bank a ay1 ay2 cay cs we cas ras cke clk t0 ck3 t t1 t2 t8 t4 t3 t5 t6 t7 t11 t9 t10 t12 t13 bank a read command activate command bank a raz raz caz spt03922 burst length = 4, cas latency = 3 t19 t16 t15 t14 t17 t18 t20 t21 t22
hyb39s512400/800/16at(l) 512-mbit synchronous dram infineon technologies 41 16. random column write (page within same bank) 16.1 cas latency = 2 dby1 addr. bs dq dqm ap activate command z hi bank b rbw rbw command write command bank b write bank b dbw0 dbw1 cbw cbx write bank b command dbw3 dbw2 dbx0 dbx1 dby0 cby cs we cas ras cke clk t0 ck2 t t1 t2 t8 t4 t3 t5 t6 t7 t11 t9 t10 t12 t13 precharge command bank b dby2 dby3 activate command bank b rbz rbz spt03923_2 read bank b command cbz burst length = 4, cas latency = 2 t19 t16 t15 t14 t17 t18 t20 t21 t22 dbz1 dbz0 dbz2 dbz3
hyb39s512400/800/16at(l) 512-mbit synchronous dram infineon technologies 42 16.2. cas latency = 3 command write bank b cbz dbw0 addr. bs dq dqm ap bank b activate command z hi rbz rbz command bank b dbw3 dbw1 dbw2 write bank b command dbx0 dbx1 cbx write dby1 dby0 dby2 precharge command bank b dby3 cby cs we cas ras cke clk t0 ck3 t t1 t2 t8 t4 t3 t5 t6 t7 t11 t9 t10 t12 t13 command bank b dbz0 activate command bank b write dbz1 rbz rbz cbz spt03924 burst length = 4, cas latency = 3 t19 t16 t15 t14 t17 t18 t20 t21 t22
hyb39s512400/800/16at(l) 512-mbit synchronous dram infineon technologies 43 17. random row read (interleaving banks) with precharge 17.1 cas latency = 2 ax2 t bs addr. dq dqm ap bank b activate command hi-z command read bank b rbx rbx rcd t cbx read activate bank a command command bank b command bx2 bx0 ac2 bx1 bank a activate bx3 bx4 rax rax command precharge bank b bx6 bx5 bx7 ax0 ax1 cax rby rby cs we cas ras cke clk t0 high t ck2 t1 t2 t8 t4 t3 t5 t6 t7 t11 t9 t10 t12 t13 spt03925_2 bank b command ax5 ax3 ax4 read ax6 ax7 cby by1 by0 burst length = 8, cas latency = 2 t19 t16 t15 t14 t17 t18 t20 t21 t22 rp t
hyb39s512400/800/16at(l) 512-mbit synchronous dram infineon technologies 44 17.2 cas latency = 3 activate command bank a addr. dqm dq ap bs read bank b command command bank b activate hi-z bx1 bx0 cbx rbx rcd t rbx t ac3 activate command bank b bx6 bank a command read bx4 bx3 bx2 bx5 bank b precharge command ax0 bx7 ax2 ax1 rax cax rax rp t rby rby precharge bank a command ax7 read bank b command ax5 ax4 ax3 ax6 spt03926 by0 cby t7 we cas ras cs cke clk high ck3 t t0 t1 t2 t3 t4 t6 t5 t16 t8 t9 t10 t11 t14 t12 t13 t15 burst length = 8, cas latency = 3 t18 t17 t19 t20 t21 t22
hyb39s512400/800/16at(l) 512-mbit synchronous dram infineon technologies 45 18. random row write (interleaving banks) with precharge 18.1 cas latency = 2 dbx4 dax1 bs ap addr. dq dqm activate command bank a hi-z write command bank a dax0 rax rax rcd t cax command command bank b bank a command dax4 dax2 dax3 bank b activate dax5 dax6 rbx rbx command precharge bank a write dbx0 dax7 dbx1 activate dbx2 dbx3 cbx ray ray clk cke cs ras cas we t0 high ck2 t t1 t2 t8 t4 t3 t5 t6 t7 t11 t9 t10 t12 t13 command bank a spt03927_2 command precharge bank b dbx7 dbx5 dbx6 write day0 day1 cay wr t day4 day3 day2 t19 burst length = 8, cas latency = 2 t16 t15 t14 t17 t18 t20 t21 t22 wr t rp t
hyb39s512400/800/16at(l) 512-mbit synchronous dram infineon technologies 46 18.2 cas latency = 3 dax4 addr. dqm dq ap bs command bank a bank a activate command hi-z write dax0 dax1 dax3 dax2 rax rcd t rax cax dbx4 dbx0 write command bank b bank b activate command dax6 dax5 dax7 precharge command bank a dbx2 dbx1 dbx3 cbx rbx rbx wr t rp t command bank a activate command bank a write dbx5 dbx6 day0 dbx7 precharge bank b command spt03928 day1 day2 day3 wr ray t cay ray cas ras cke clk we cs t2 high ck3 t t0 t1 t4 t3 t5 t6 t15 t7 t8 t9 t10 t11 t12 t13 t14 burst length = 8, cas latency = 3 t19 t17 t16 t18 t21 t20 t22
hyb39s512400/800/16at(l) 512-mbit synchronous dram infineon technologies 47 19. precharge termination of a burst 19.1 cas latency = 2 command activate bank a t14 bs write data is masked. of a write burst. precharge termination addr. dq dqm ap command bank a activate hi z bank a write command dax0 dax1 rax rax cax command bank a command precharge bank a dax3 dax2 activate ray rp t ray ay0 command bank a read bank a precharge command ay1 ay2 cay rp t t3 cs we cas ras cke clk t0 high ck2 t t1 t2 t4 t5 t7 t6 t8 t10 t9 t11 t13 t12 precharge termination of a read burst. spt03933 bank a command precharge command bank a read az0 az1 raz caz raz az2 rp t burst length = 8 or full page, cas latency = 2 t20 t17 t15 t16 t18 t19 t21 t22
hyb39s512400/800/16at(l) 512-mbit synchronous dram infineon technologies 48 20. full page burst operation 20.1 full page burst read, cas latency = 2 bs - page address back to zero from the highest order the burst counter wraps during this time interval. addr. dqm dq ap ~ ~ hi-z command command bank a read bank a activate bank b bank b command command ax activate activate ax +1 ax ~ ~ +2 ax rax rax cax ~ ~ ~ ~ rbx rbx ~ ~ ~ ~ ~ ~ ~ ~ spt03929 bursting beginning with the starting address. burst stop command the burst counter increments and continues terminate when the burst length is satisfied; full page burst operation does not bank b command ax read - 2ax 11 ax + bx bx +1 bx +2 + bx 3 + bx 4 cbx bank b command activate command bank b precharge bx 5 bx+ 6 + rby t rp rby cas ras cke clk cs we ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ high ck2 t t0 t1 t2 ~ ~ ~ ~ t3 t4 ~ ~ ~ ~ t5 t6 t15 t11 t7 t8 t10 t9 t13 t12 t14 burst length = full page, cas latency = 2 t16 t17 t18 t19 t20 t21 t22
hyb39s512400/800/16at(l) 512-mbit synchronous dram infineon technologies 49 20. full page burst operation 20.2 full page burst write, cas latency = 3 t14 bx full page burst operation does not terminate when the burst length is satisfied; bursting beginning with the starting address. the burst counter increments and continues bs command bank a ap dqm dq addr. command activate bank a hi-z read rax rax cax page address back to zero during this time interval. the burst counter wraps from the highest order activate activate bank b bank b command command ax ax 1 + 2 ax + ax ~ ~ ~ ~ - rbx rbx ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ax read bank b command ax 21 - ax 1 + bx bx 1 + cbx t3 clk cke cs ras we cas t0 high ck3 t t1 t2 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ t4 t5 ~ ~~ ~ ~ ~ t7 t6 t8 ~ ~ t10 t9 t11 t13 t12 spt03930 bank b command activate bank b precharge command burst stop command + +2 bx bx 34 + 5 + bx rby t rrd rby t20 burst length = full page, cas latency = 3 t17 t15 t16 t18 t19 t21 t22
hyb39s512400/800/160at(l) 512-mbit synchronous dram infineon technologies 50 attention please ! as far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. this infomation describes the type of components and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. for questions on technology, delivery and prices please contact infineon technologies offices in munich or the infineon technologies sales offices and representatives worldwide. due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office or representative. packing please use the recycling operators known to you. we can help you - get in touch with your nearest sales office. by agreement we will take packing material back, if it is sorted. you must bear the costs of transport. for packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. components used in life-support devices or systems must be expressly authorized for such purpose! ciritcal components 1 of infineon technologies, may only be used in life- support devices or systems 2 with the express written approval of infineon technologies. 1. a critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life- support device or system, or to affect the safety or effectiveness of that device or system. 2. life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. if they fail, it is reasonable to assume that the health of the user may be endangered.

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